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U2896B
Modulation PLL for GSM, DCS and PCS Systems
Description
The U2896B is a monolithic integrated circuit. It is realized using TEMIC's advanced silicon bipolar UHF5S technology. The device integrates a mixer, an I/Q modulator, a phase-frequency detector (PFD) with two synchronous programmable dividers, and a charge pump. The U2896B is designed for cellular phones such as GSM900, DCS1800, and PCS1900, applying a transmitter architecture at which the VCO operates at the TX output frequency. No duplexer is needed since the out-of-band noise is very low. The U2896B exhibits low power consumption. Broadband operation gives high flexibility for multi-band frequency mappings. The IC is available in a shrinked small-outline 36-pin package (SSO36). Electrostatic sensitive device. Observe precautions for handling.
Features
D Supply voltage range 2.7 V to 5.5 V D Current consumption 50 mA D Power-down functions D High-speed PFD and charge pump (CP) D Small CP saturation voltages (0.5/0.6 V) D Programmable dividers and CP polarity D Low-current standby mode
Benefits
D D D D D D
Novel TX architecture saves filter costs Extended battery operating time without duplexer Less board space (few external components) VCO control without voltage doubler Small SSO36 package One device for all GSM bands
Block Diagram
VS1 GND1 I NI 6 MDLO 3 NMDLO 4 MDO NMDO 7 8 Modulator 51 2 Q NQ 36 LO VRef 90 Mixer 24 31 29 28 30 35 23 PU NMIXOMIXO PUMIX MIXLO 32 33 34 25
NMIXLO VS3 RF NRF GND3
22 ND NND 15 RD NRD 16 R 1:2 Mode control 17 MC 27 26 13 CPCL 14 CPCH
14891
21
N 1:2 MUX PFD Charge pump
10 11 12
VSP CPO GNDP
VS2 GND2
Figure 1. Block diagram
Rev. A1, 18-Sep-98
1 (13)
Preliminary Information
U2896B
Ordering Information
Extended Type Number U2896B-MFCG3 Package SSO36 Remarks Taped and reeled
Pin Description
I NI MDLO NMDLO GND1 VSI 1) MDO NMDO SUB 1 2 3 4 5 6 7 8 9 36 Q 35 NQ 34 PUMIX 33 MIXO 32 NMIXO 31 VS3 1) 30 GND3 29 RF 28 NRF 27 VS2 1) 26 GND2 25 MIXLO 24 NMIXLO 23 PU 22 ND 21 NND 20 n.c. 19 n.c.
14892
VSP 10 CPO 11 GNDP 12 CPCL 13 CPCH 14 RD 15 NRD 16 MC 17 n.c. 18
Figure 2. Pinning
2 (13)
Preliminary Information
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14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
1)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13
Function In-phase base band-input Complementary to I I/Q-modulator LO input Complementary to MDLO Ground Supply I/Q modulator I/Q modulator Complementary to MDO Substrate, connected to GND Supply charge pump Charge pump output Ground Charge pump current control GSM1800 CPCH Charge pump current control GSM900 RD R-divider input NRD Complementary to RD MC Mode control n.c. Not connected n.c. Not connected n.c. Not connected NND Complementary to ND ND N-divider input PU Power-up. whole chip, except mixer NMIXLO Complementary to MIXLO MIXLO Mixer LO input GND2 Ground 1) VS2 Supply (MISC) NRF Complementary to RF RF Mixer RF input GND3 Ground VS3 1) Supply mixer NMIXO Complementary to MIXO MIXO Mixer output PUMIX Power-up mixer NQ Complementary to Q Q Quad-phase base-band input
Symbol I NI MDLO NMDLO GND1 VS1 1) MDO NMDO SUB VSP CPO GNDP CPCL
Between the Pins VS1, VS2 and VS3 the allowed maximum voltage is 200 mV Rev. A1, 18-Sep-98
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1) 2) VS = 2.7 to 5.5 V, Tamb = -20C to +85C, final test at 25C
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Electrical Characteristics Thermal Resistance Operating Range
Parameters Junction ambient SSO36 Supply voltage Supply voltage Ambient temperature Parameters Symbol RthJA Symbol VVS# VVSP Tamb | ICPC | Tamb Tstg 5 -20 to +85 -40 to +125 Value 2.7 to 5.5 2.7 to 5.5 -20 to +85 Value 130 Unit K/W Unit V V C mA C C
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Absolute Maximum Ratings
Parameters Supply voltage VS1, VS2, VS3 Supply voltage charge pump VSP Voltage at any input Current at any input / output pin except CPC CPC output currents Ambient temperature Storage temperature Symbol VVS# VVSP VVi# | II# | | IO# |
Rev. A1, 18-Sep-98 Active (VPU = VS) Standby (VPU = 0) Supply current IVS2 pp y Active (VPU = VS) Standby (VPU = 0) Supply current IVS3 pp y Active (VPUMIX = VS) Standby (VPUMIX = 0) Supply current IVSP 1) Active (VPU = VS, CPO open) Standby (VPU = 0) N & R divider inputs ND, NND & RD, NRD N:1 divider frequency 50-W source R:1 divider frequency 50-W source Input impedance Active & standby Input sensitivity 50-W source Input capacitance Active & standby Parameters DC supply Supply voltages VS# Supply voltage VSP Supply current IVS1 pp y Mean value, measured with FND = 151 MHz, FRD = 150 MHz, current vs. time, see page 6, figure 3 For optimized noise performance this voltage level may be higher VVS1 = VVS2 = VVS3 Test Conditions / Pin fND fRD ZRD, ZND VRD, VND CRD, CND Symbol IVSPY VVS# VVSP IVS1A IVS1Y IVS2A IVS2Y IVS3A IVS3Y IVSPA 2.7 VVS# - 0.3
Preliminary Information
vV 5.5 -0.5 v V v V
Min.
100 100 1 5 2)
Vi#
Value
2
Typ.
1.4
13
17
17
VSP
VS#
U2896B
+5.5
Max.
200 0.5
600 600
5.5 5.5 22 20 22 20 17 30 1.8
20
MHz MHz kW mVrms pF
Unit V V V mA
Unit
mA
mA
mA
V V mA
mA
mA
mA
mA
3 (13)
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4) 5)
6) 7)
VS = 2.7 to 5.5 V, Tamb = -20C to +85C, final test at 25C
Electrical Characteristics (continued)
U2896B
4 (13) AC voltage Differential (preferres) I/Q modulator LO input MDLO MDLO Frequency range Input impedance Active & standby Input level 50-W source I/Q modulator outputs MDO, NMDO DC current VMDO, VNMDO = VS Internal pull-up resistor Voltage compliance VMDO, VNMDO = VC MDO output level 615 W to VS 6) (differential) 1.5 pF external load Carrier suppression 6) Sideband suppression 6) IF spurious 6) fLO 3 fmod 6) Noise @ 400 kHz off carrier Frequency range Mixer (900 MHz) RF input level 900 MHz Output resistance LO-spurious at @ P9MIXLO = -10 dBm RF/NRF port @ P9RF = -15 dBm MIXLO input level 0.05 to 2 GHz MIXO Frequency range Output level 7) differen- @ P9MIXLO = -15 dBm tial Carrier suppression @ P9MIXLO = -15 dBm MD_IQ AC voltage 5) Parameters Test Conditions / Pin Phase-frequency detector (PFD) PFD operation fND = 600 MHz, N = 2 fRD = 600 MHz, R = 2 Frequency comparison fND = 600 MHz, N = 2 only 4) fRD = 450 MHz, R = 2 I/Q modulator baseband inputs I, NI & Q, NQ DC voltage Referred to GND Frequency range Referred to GND IMDO, INMDO RMDO, RNMDO VCMDO, VCNMDO VS - 0.7 PMDO 40 VI, VNI, VQ, VNQ P9RF RMIXO, RNMIXO SP9RF fIO ACI, ACNI, ACQ, ACNQ ACDI, ACDQ CS9MIXO P9MIXLO fMIXO P9MIXO Symbol CSMDO SSMDO SPMDO NMDO fMDO fMDLO ZMDLO PMDLO fPFD fFD Min. 1.35 -20 -22 50 -23 100 -32 -35 -14 100 50 0 VS1/2 Typ. 650 -35 -40 -50 0.8 615 400 200 3 -11 80
PFD can be used as a frequency comparator until 300 MHz for loop acquisition Single-ended operation (complementary baseband input is AC-grounded) leads to reduced linearity (degrading suppression of odd harmonics) With typical drive levels at MDLO- & I/Q-inputs -1 dB compression point C = 1.5 pF to GND
Preliminary Information
VS1/2 + 0.1 1 Rev. A1, 18-Sep-98 Max. -45 -115 450 -12 450 -40 -17 450 400 300 5.5 60 -5 dBc dBc dBc dBc/Hz MHz dBm MHz mVrms V mVrms mVpp MHz mVpp MHz kW dBm MHz MHz dBm dBm Unit mA dBc
W W
V
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VS = 2.7 to 5.5 V, Tamb = -20C to +85C, final test at 25C
Rev. A1, 18-Sep-98
8) 9) 10)
Electrical Characteristics (continued)
Parameters Test Conditions / Pin Symbol Mixer (1900 MHz) Output resistance RMIXO, RNMIXO RF input level 0.5 to 2 GHz P19RF LO-spurious at @ P19MIXLO = -10 dBm SP19RF RF/NRF ports @ P19RF = -15 dBm MIXLO input level 0.05 to 2 GHz P19MIXLO MIXO Output level 8) differen- @ P19MIXLO = -17 dBm P19MIXO tial Carrier suppression @ P19MIXLO = -17 dBm CS19MIXO Charge-pump output CPO (VVSP = 5 V; VCPO = 2.5 V) Pump-current p pulse RCPCH 9) = 4.7 k | ICPO_H | p RCPCL 10) = 2.4 k | ICPO_L | Sensivity to VVSP SICPO DI DVVSP | | CPO | | I CPO V VSP
Mode control Sink current VMC = VS IMC Power-up input PU (power-up for all functions, except mixer) Settling time Output power within 10% SPU of steady state values High level Active VPUH Low level Standby VPUL High-level current Active, VPUH = 2.2 V IPUH Low-level current Standby, VPUL = 0.4 V IPUL Power-up input PUMIX (power-up for mixer only) Settling time Output power within 10% tsetl of steady state values High level Active VPUMIXH Low level Standby VPUMIXL High-level current Active, VPUMIXH = 2.2 V IPUMIXH Low-level current Standby, IPUMIXL VPUMIXL = 0.4 V
VCPO voltage range
- 1 dB compression point C = 1.5 pF to GND RCPCH: external resistor to GND for charge-pump current control (MODE 1, 5, only Pin 14 active) RCPCL: external resistor to GND for charge-pump current control (MODE 2, 3, 4, only Pin 13 active)
| ICPO | degradation < 10% (VVSP = 2.7 V to 5 V)
Preliminary Information
VCPO Min. -20 -22 -23 2.0 0 0.1 -1 2.0 0 0.5 1.4 3 -1 Typ. 650 60 70 5 5 2 4 VVSP-0.6
U2896B
Max.
-12
-17 -40
0.4 70 20
0.4 70 20
2.6 5 0.1
10
10
mVrms
dBm
dBm dBm
Unit
dBc
mA mA -
mA mA
mA mA
mA
5 (13)
ms ms
W
V V V V V
U2896B
Supply Current of the Charge Pump IVSP vs. Time
Due to the pulsed operation of the charge pump, the current into the charge-pump supply pin VSP is not constant. Depending on I (see figure 5) and the phase difference at the phase detector inputs, the current IVSP over time varies. Basically, the total current is the sum of the quiescent current, the charge-/discharge current, and - after each phase comparison cycle - a current spike (see figure 3). Internal current |ICPC| vs. RCPC RCPC 19.2 kW 9.6 kW 4.8 kW 2.4 kW (typical values) |ICPCO| 0.5 mA 1 mA 2 mA 4 mA ICPCO ICPO -ICPCO
14913
Up Down 2.5 ICPCO IVSP 1.5 I CPCO I t
t
Figure 3. Supply current of the charge pump
Mode Selection
The device can be programmed to different modes via an external resistor RMODE (including short, open) from Pin MC to VS2. The mode is distinguished from specific N-, R-divider ratios, and the polarity of the charge-pump selection. Mode Selection Mode Resistance between Pin MC and Pin VS2 0 (<50 W) 2.7 kW (5%) 10 kW (5%) 47 kW (5%) (> MW) 1:1 1:1 1:1 2:1 2:1 1:1 1:1 2:1 2:1 2:1 N-Divider R-Divider CPO Current Polarity 4) fn < fR 1) fn > fR 1) Application CPCH active CPCL active
1 2 3 4 5
1) 2) 3) 4)
sink source source source sink
source sink sink sink source
t.b.d. t.b.d. t.b.d. PCN/ PCS 2) GSM 3)
x x x x x
Frequencies referred to PFD input LO frequencies below VCO frequency LO frequencies above VCO frequency Sink current into Pin CPO. Source: current out from Pin CPO.
6 (13)
Rev. A1, 18-Sep-98
Preliminary Information
U2896B
Equivalent Circuits at the IC's Pins
2 x 615 W VBias_MDLO MDO NMDO 2230 I,Q MDLO NI, NQ VRef_input VRef_MDLO VRef_output 2230 VS1
GND Baseband inputs LO input Figure 4. I/Q modulator Output
14893
1 k RF 890 NRF VBias_RF 890 MIXLO
1 k VBias_LO 1.6 k 1.6 k 650 W NMIXO 650 W MIXO VS3
VRef_RF
VRef_LO
GND RF input LO output Figure 5. Mixer Output
14894
4 4 I
VSP
up Ref CPCL CPCH n = Transistor with an emitter area-factor of "n" VRef n n Ref
down
CPO I GNDP
14896
Figure 6. Charge pump
Rev. A1, 18-Sep-98
7 (13)
Preliminary Information
U2896B
VS2
ND/RD 2 k NND/NRD 2 k PU, PUMIX 20 k
VRef_div
GND
14899
GND
14897
Figure 7. Dividers VS2
Figure 8. Power-up
N-divider Logic R-divider MUX MC 2x 60 A
C (U) 0.5 pF @ 2 V C (U) is a non-linear junction capacitance
14900
Figure 10. ESD-protection diodes
GND Figure 9. Mode control
14898
8 (13)
Rev. A1, 18-Sep-98
Preliminary Information
U2896B
Application Hints
Interfacing For some of the baseband ICs it may be necessary to reduce the I/Q voltage swing so that it can be handled by the U2896B. In those cases, the following circuitry can be used. Mode Control
U2896B VS2
U2896B VS2
R1 I R1 Baseband IC NI Q R1 NQ R1
14901
I R2 C NI Q R2 C NQ U2896B VS2 RMode U2896B VS2 U2896B RMode RMode1 MC a) any single mode b) any 2 modes RMode2 MC
Figure 11. Interfacing the U2896B to I/Q baseband circuits
Due to a possible current offset in the differential baseband inputs of the U2896B the best values for the carrier suppression of the I/Q modulator can be achieved with voltage driven I/NI-, and Q/NQ-inputs. A value of Rsource = R2/2*RS 1.5 kW should be realized. RS is the sum of R1 (above drawing) and the output resistance of the baseband IC.
RMode MC c) any mode & mode 5
MC 36 k or 10 k d) mode 5 & mode 3 or mode 4
14895
v
Figure 12. Application examples for programming different modes
Rev. A1, 18-Sep-98
9 (13)
Preliminary Information
U2896B
Test Circuit
R1 V4 1.35V R2 V5 450 mVpp V2 450 mVpp R11 R12 V3 1.35V
1 2
C1
36 35 34 33 32 31
C9 C7 C8
3 4 5
3V
200MHz -10dBm
R3
C2
C3 3V
6 7 8 9 U2896B
3V
30 29 28 27
C12 C10 C11 900MHz -15dBm
3V, 5V C4
10 11
R4 V7 1.5V R5
3V
26 25 24 23 22 21 20 n.c. 19 n.c.
14903
C13 C14 R13 1100MHz -15dBm
12 13 14
R6 C5
3V C15 C16 R14 200MHz -15dBm
15 16 17
200.1MHz -15dBm
R7
C6
3V R8 R9 R10
n.c. 18
Figure 13. Test circuit
10 (13)
Rev. A1, 18-Sep-98
Preliminary Information
U2896B
Application Circuit for DCS1800 (1710 - 1785 MHz)
R1 R9
1
Baseband R2 R3 C1
36 35 34 33 32 31
C12
R8 R10
Baseband
2
2nd LO -10dBm C2 C3
3 4 5
3V
C4 3V
6 7 8 9
3V C13
30 29 28 U2896B 27
C16 C14 C15 VCO 880 to 915MHz 1710 to 1785MHz -20dBm 3V
3V, 5V
10
Tuning voltage R4 C7 R5 C6 C5
11 12 13 14
R6 C9 C8 L1 C10 R7 3V L2
26 25 24 23 22 21 20 19
14904
C17 C18 1st LO -15dBm
3V C19 C20 L3 C29
15
C11
16 17
n.c. 18
n.c. n.c.
Figure 14. Application circuit
Measurements
Modulation-Loop Settling Time
As valid for all PLL loops the settling time depends on several factors. The following figure is an extraction from measurements performed in an arrangement like the application circuit. It shows that a loop settling time of a few ms can be achieved.
Modulation Spectrum & Phase Error
CPC: 1 k to GND
CPC `open'
Vertical: VCO tuning voltage 1 V/Div Horizontal: Time 1 ms/Div
Rev. A1, 18-Sep-98
11 (13)
Preliminary Information
U2896B
Package Information
Package SSO36
Dimensions in mm
9.6 9.1 5.6 5.2 4.5 4.3
1.3 0.2 0.5 8.45 36 19 0.15 0.05 0.12 6.6 6.3
technical drawings according to DIN specifications
13047
1
18
12 (13)
Rev. A1, 18-Sep-98
Preliminary Information
U2896B
Ozone Depleting Substances Policy Statement
It is the policy of TEMIC Semiconductor GmbH to 1. Meet all present and future national and international statutory requirements. 2. Regularly and continuously improve the performance of our products, processes, distribution and operating systems with respect to their impact on the health and safety of our employees and the public, as well as their impact on the environment. It is particular concern to control or eliminate releases of those substances into the atmosphere which are known as ozone depleting substances ( ODSs). The Montreal Protocol ( 1987) and its London Amendments ( 1990) intend to severely restrict the use of ODSs and forbid their use within the next ten years. Various national and international initiatives are pressing for an earlier ban on these substances. TEMIC Semiconductor GmbH has been able to use its policy of continuous improvements to eliminate the use of ODSs listed in the following documents. 1. Annex A, B and list of transitional substances of the Montreal Protocol and the London Amendments respectively 2 . Class I and II ozone depleting substances in the Clean Air Act Amendments of 1990 by the Environmental Protection Agency ( EPA) in the USA 3. Council Decision 88/540/EEC and 91/690/EEC Annex A, B and C ( transitional substances ) respectively. TEMIC Semiconductor GmbH can certify that our semiconductors are not manufactured with ozone depleting substances and do not contain such substances.
We reserve the right to make changes to improve technical design and may do so without further notice. Parameters can vary in different applications. All operating parameters must be validated for each customer application by the customer. Should the buyer use TEMIC products for any unintended or unauthorized application, the buyer shall indemnify TEMIC against all claims, costs, damages, and expenses, arising out of, directly or indirectly, any claim of personal damage, injury or death associated with such unintended or unauthorized use. TEMIC Semiconductor GmbH, P.O.B. 3535, D-74025 Heilbronn, Germany Telephone: 49 ( 0 ) 7131 67 2594, Fax number: 49 ( 0 ) 7131 67 2423
Rev. A1, 18-Sep-98
13 (13)
Preliminary Information

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